Computing with memory

Computing with memory platforms are typically used to provide the benefit of hardware reconfigurability. Reconfigurable computing platforms offer advantages in terms of reduced design cost, early time-to-market, [[rapid prototyping]] and easily customizable hardware systems. FPGAs present a popular reconfigurable computing platform for implementing digital circuits. They follow a purely spatial computing model. Since their inception in 1985, the basic structure of the FPGAs has continued to consist of two-dimensional array of configurable logic blocks (CLBs) and a programmable interconnect matrix.K.Compton and S. Hauck, "Computing: A Survey of systems and software", ''ACM Surveys'', Vol. 34, No. 2, June, 2002. FPGA performance and power dissipation is largely dominated by the elaborate programmable interconnect (PI) architecture.S. M. Trimberger, ''Field Programmable Gate Array Technology'', Norwell, MA: Kluwer, 1994.A. Rahman, S. Das, A. P. Chandrakasan, R. Reif, "Wiring Requirement and Three-Dimensional Integration Technology for Field Programmable Gate Arrays", ''IEEE Trans. on Very Large Scale Integration Systems'', Vol. 11, No. 1, February, 2003. An effective way of reducing the impact of the PI architecture in FPGA is to place small LUTs in close proximity (referred as clusters) and to allow intra-cluster communication using local interconnects. Due to the benefits of a clustered FPGA architecture, major FPGA vendors have incorporated it in their commercial products.[https://www.xilinx.com Xilinx Corporation][https://www.altera.com Altera Corporation] Investigations have also been made to reduce the overhead due to PI in fine-grained FPGAs by mapping larger multi-input multi-output LUTs to embedded memory blocks. Although it follows a similar spatial computing model, part of the logic functions are implemented using embedded memory blocks while the remaining part is realized using smaller LUTs.J. Cong and S. Xu, "Technology Mapping for FPGAs with Embedded Memory Blocks", Symposium on Field Programmable Gate Array, 1998. Such a heterogeneous mapping can improve the area and performance by reducing the contribution of programmable interconnects.

Computing with memory platforms are typically used to provide the benefit of hardware reconfigurability. Reconfigurable computing platforms offer advantages in terms of reduced design cost, early time-to-market, [[rapid prototyping]] and easily customizable hardware systems. FPGAs present a popular reconfigurable computing platform for implementing digital circuits. They follow a purely spatial computing model. Since their inception in 1985, the basic structure of the FPGAs has continued to consist of two-dimensional array of configurable logic blocks (CLBs) and a programmable interconnect matrix.K.Compton and S. Hauck, "Computing: A Survey of systems and software", ''ACM Surveys'', Vol. 34, No. 2, June, 2002. FPGA performance and power dissipation is largely dominated by the elaborate programmable interconnect (PI) architecture.S. M. Trimberger, ''Field Programmable Gate Array Technology'', Norwell, MA: Kluwer, 1994.A. Rahman, S. Das, A. P. Chandrakasan, R. Reif, "Wiring Requirement and Three-Dimensional Integration Technology for Field Programmable Gate Arrays", ''IEEE Trans. on Very Large Scale Integration Systems'', Vol. 11, No. 1, February, 2003. An effective way of reducing the impact of the PI architecture in FPGA is to place small LUTs in close proximity (referred as clusters) and to allow intra-cluster communication using local interconnects. Due to the benefits of a clustered FPGA architecture, major FPGA vendors have incorporated it in their commercial products.[https://www.xilinx.com Xilinx Corporation][https://www.altera.com Altera Corporation] Investigations have also been made to reduce the overhead due to PI in fine-grained FPGAs by mapping larger multi-input multi-output LUTs to embedded memory blocks. Although it follows a similar spatial computing model, part of the logic functions are implemented using embedded memory blocks while the remaining part is realized using smaller LUTs.J. Cong and S. Xu, "Technology Mapping for FPGAs with Embedded Memory Blocks", Symposium on Field Programmable Gate Array, 1998. Such a heterogeneous mapping can improve the area and performance by reducing the contribution of programmable interconnects.

Contrary to the purely spatial computing model of FPGA, a reconfigurable computing platform that employs a temporal computing model (or a combination of both temporal and spatial) has also been investigated S. Paul and S. Bhunia, "Reconfigurable Computing Using Content Addressable Memory for Improved Performance and Resource Usage", Design Automation Conference, 2008.S. Paul, S. Chatterjee, S. Mukhopadhyay and S. Bhunia, "Nanoscale Reconfigurable Computing Using Non-Volatile 2-D STTRAM Array", International Conference on Nanotechnology, 2009. in the context of improving performance and energy over conventional FPGA. These platforms, referred as "memory-based computing" (MBC), use dense two-dimensional memory array to store the LUTs. Such frameworks rely on breaking a complex function (''f'') into small sub-functions; representing the sub-functions as multi-input, multi-output LUTs in the memory array; and evaluating the function ''f'' over multiple cycles. MBC can leverage on the high density, low power and high performance advantages of nanoscale memory.

Contrary to the purely spatial computing model of FPGA, a reconfigurable computing platform that employs a temporal computing model (or a combination of both temporal and spatial) has also been investigatedS. Paul and S. Bhunia, "Reconfigurable Computing Using Content Addressable Memory for Improved Performance and Resource Usage", Design Automation Conference, 2008.S. Paul, S. Chatterjee, S. Mukhopadhyay and S. Bhunia, "Nanoscale Reconfigurable Computing Using Non-Volatile 2-D STTRAM Array", International Conference on Nanotechnology, 2009. in the context of improving performance and energy over conventional FPGA. These platforms, referred as "memory-based computing" (MBC), use dense two-dimensional memory array to store the LUTs. Such frameworks rely on breaking a complex function (''f'') into small sub-functions; representing the sub-functions as multi-input, multi-output LUTs in the memory array; and evaluating the function ''f'' over multiple cycles. MBC can leverage on the high density, low power and high performance advantages of nanoscale memory.