Compute Express Link

Apr 20, 2026 - 22:46
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Compute Express Link

Device types

← Previous revision Revision as of 17:14, 20 April 2026
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* Type 1 (CXL.io and CXL.cache) – coherently access host memory, specialized accelerators (such as smart [[network interface card|NIC]], PGAS NIC, and NIC Atomics) with no local memory. Devices rely on coherent access to host CPU memory.
* Type 1 (CXL.io and CXL.cache) – coherently access host memory, specialized accelerators (such as smart [[network interface card|NIC]], PGAS NIC, and NIC Atomics) with no local memory. Devices rely on coherent access to host CPU memory.
* Type 2 (CXL.io, CXL.cache and CXL.mem) – coherently access host memory and device memory, general-purpose accelerators ([[graphics processing unit|GPU]], [[ASIC]] or [[FPGA]]) with high-performance [[GDDR]] or [[High Bandwidth Memory|HBM]] local memory. Devices can coherently access host CPU's memory and/or provide coherent or non-coherent access to device local memory from the host CPU.
* Type 2 (CXL.io, CXL.cache and CXL.mem) – coherently access host memory and device memory, general-purpose accelerators ([[graphics processing unit|GPU]], [[ASIC]] or [[FPGA]]) with high-performance [[GDDR]] or [[High Bandwidth Memory|HBM]] local memory. Devices can coherently access host CPU's memory and/or provide coherent or non-coherent access to device local memory from the host CPU.
* Type 3 (CXL.io and CXL.mem) – allow the host to access and manage attached device memory, memory expansion boards and persistent memory. Devices provide host CPU with low-latency access to local DRAM or byte-addressable non-volatile storage.
* Type 3 (CXL.io and CXL.mem) – allow the host to access and manage attached device memory, memory expansion boards and persistent memory. Devices provide host CPU with low-latency access to local DRAM or byte-addressable non-volatile storage.While Type 3 memory expansion devices are currently targeted predominantly at enterprise and datacenter environments, architectural proposals such as the open-source XMM Architecture suggest adapting CXL.mem for consumer desktop systems. This approach, known as single-node memory disaggregation, relocates the memory controller from the CPU die to a PCIe Add-in Card (AIC), allowing desktop systems to bypass the physical routing limitations of parallel DDR interfaces and achieve unified memory/>


Type 2 devices implement two memory coherence modes, managed by device driver. In device bias mode, device directly accesses local memory, and no caching is performed by the CPU; in host bias mode, the host CPU's cache controller handles all access to device memory. Coherence mode can be set individually for each 4 KB page, stored in a translation table in local memory of Type 2 devices. Unlike other CPU-to-CPU memory coherency protocols, this arrangement only requires the host CPU memory controller to implement the cache agent; such asymmetric approach reduces implementation complexity and reduces latency.
Type 2 devices implement two memory coherence modes, managed by device driver. In device bias mode, device directly accesses local memory, and no caching is performed by the CPU; in host bias mode, the host CPU's cache controller handles all access to device memory. Coherence mode can be set individually for each 4 KB page, stored in a translation table in local memory of Type 2 devices. Unlike other CPU-to-CPU memory coherency protocols, this arrangement only requires the host CPU memory controller to implement the cache agent; such asymmetric approach reduces implementation complexity and reduces latency.
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